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Bhanu Kapoor, PhD

Adjunct Professor, School of Technology

Bhanu Kapoor, PhD photo

Teaching Experience:

  • Southern Methodist University, Adjunct Faculty, Department of Computer Science and Engineering
  • Southern Methodist University, Executive Program in Security Engineering at L3 Systems
  • Raytheon and Lockheed Martin – courses in computer architecture, border and transportation security, cryptography, data and network security, computer forensics and fault-tolerant computing
  • Adjunct Faculty, Computer Science, University of Texas - Computer Organization, Advanced Requirements Engineering, Object-oriented Analysis and Design, Modeling and Simulation and Optimization Theory and Practice  

Dissertation:

  • Synthesis and analysis of delay fault testable digital circuits

Education:

  • BTech, Electrical Engineering, Indian Institute of Technology,
  • MS, Computer Science, Southern Methodist University
  • PhD, Computer Science, Southern Methodist University

Research Areas of Interest:

  • Low Power Chip Design, Parallel Computing, Information Security, Quantum Computing

Publications:

  • Neha Kishore and Bhanu Kapoor, Attacks on and Advances in Secure Hash Algorithms, accepted in IAENG International Journal of Computer Science (IJCS, ISSN: 1819-9224). Published August 27, 2016.
  • N. Kishore and B. Kapoor, Faster File Imaging Framework for Digital Forensics, 4th International Conference on Advanced Computer, Communications, and Control, April 1-2, 2015, Mumbai, India.
  • N. Kishore and B. Kapoor, CUDA Implementation of RSHA-1 and Code Optimization, GPU Technology Conference (GTC). March 17-20, 2015, San Jose, CA.
  • D. Handa and B. Kapoor, PBlock- an Energy Efficient Parallel Approach for Faster File and Disk Encryption using Parallel Independent Feistel Cipher Structure, accepted for publication in International Journal of Applied Engineering Research, 2015.
  • N. Kishore, and B. Kapoor. An efficient parallel algorithm for hash computation in security and forensics applications. IEEE Xplore. Version 10.1109/IAdCC.2014.6779433. IEEE, 22 Feb. 2014. Web. 8 Apr. 2014.
  • S. Saxena, and B. Kapoor. An efficient parallel algorithm for secured data communications using RSA public key cryptography method. IEEE Xplore. IEEE, 22 Feb. 2014. Web. 8 Apr. 2014.
  • D. Handa, and B. Kapoor. (2014, February 6). PARC4: High performance implementation of RC4 cryptographic algorithm using parallelism. IEEE Xplore. Retrieved April 25, 2014.
  • D. Bagchi, K. Kaushik, and B. Kapoor, Virtual Labs for Electronics Engineering using Cloud Computing, to appear IEDEC 2013, Santa Clara, CA.
  • D. Bagchi, K. Kaushik, and B. Kapoor,“Virtual Learning System in Electronics Engineering Education, IEDEC 2012, Santa Clara, CA.
  • Design and Verification with SystemC,  IEEE 15th VLSI Design and Test Symposium,  July 09, 2011, Pune, India.  [Bhanu Kapoor, Prapanna Tiwari(Synopsys), Shireesh Verma (Conexant), Rahul Joshi (Chip Design Pvt. Ltd.)]
  • Design and Verification with SystemC,  Software- Hardware Co-design, Computer Society of India,  June 12, 2011, Chandigarh, India.  [Bhanu Kapoor]
  • Adaptive Low Power Embedded System Design and Verification: Challenges and Solutions, NASA ESA Conference on Adaptive Hardware and Systems (AHS-2011), June 6, 2011, San Diego, CA.  [Bhanu Kapoor, Prapanna Tiwari(Synopsys), Shireesh Verma (Conexant), John Goodenough (ARM)]
  • Best Practices in Designing Low Power Embedded Systems ,  Embedded Systems Conference, May 5, 2011, San Jose, CA. [Bhanu Kapoor, Prapanna Tiwari (Synopsys)]
  • Power Management Challenges,  IEEE/DATC  18th Annual Electronic Design Process Symposium, April  7, 2011, Monterey, CA. [Bhanu Kapoor, Rob Aitken (ARM)]
  • Power Management Verification Experiences in Wireless SoCs, Design Automation and Test in Europe, March 16, 2011, Grenoble, France. [ Bhanu Kapoor, Alan Hunter (ARM),  Prapanna Tiwari (Synopsys)]
  • Verification of Power-Managed Wireless SoCs,  ISQED 2011, March 15, 2011, Santa Clara, CA. [Bhanu Kapoor, Amit Kumar (CSR), Prapanna Tiwari (Synopsys)]
  • Addressing Critical Power Management Verification Issues in Low Power Designs , Design Automation and Test in Europe, March 15, 2011, Grenoble, France. [ Bhanu Kapoor,  Just Knut(Infineon/Intel), Kevin O’Brian(Synopsys), John Goodenough (ARM) ]
  • Addressing Critical Power Management Verification Issues in Low Power Designs
  • Challenges in Designing, Verifying, and Integrating Power-Managed IPs”, UBM’s DesignCon 2011, February 01, 2011, Santa Clara, CA. [ Bhanu Kapoor,  Ed Sperling (Chip Design Magazine), Prapanna Tiwari(Synopsys), Rob Aitken(ARM), Kesava Tallurupuru (MIPS) ]

Granted Patents:

  1. US 5805459, Method of measuring activity in a digital circuit, http://www.google.com/patents/US5805459
  2. US 5978509, Low power video decoder system with block-based motion compensation, http://www.google.com/patents/US5978509
  3. EP 0838956, A method and apparatus for decoding video data, http://www.google.com/patents/EP0838956A3?cl=en
  4. US 7076748, Identification and implementation of clock gating in the design of integrated circuits, http://www.google.com/patents/US7076748
  5. US 7152216, Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains, http://www.google.com/patents/US7152216
  6. US 7546559, Method of optimization of clock gating in integrated circuit designs, http://www.google.com/patents/US7546559
  7. US 7712061, Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits, http://www.google.com/patents/US7712061

Selected Professional Experience:

  • Consultant/Owner, Mimasic.
  • Technology Director, Atrenta, Inc. 
  • Texas Instruments